The present invention relates to a memory circuit, and particularly to a static type random access memory (SRAM) comprised of MOS field effect transistors (MOSFETs).
SRAMs have been widely utilized in various fields as high speed RAMs. In view of savings of external terminals, a so-called internal-synchronous SRAM has been proposed and presently subjected to practical use. In the internal-synchronous SRAM, when a change in address inputs occurs for a new access cycle, at least one control signal is generated within a SRAM and the new access cycle is initiated under control of the above at least one control signal.
For example, in the case of a read operation, after content of the address inputs has changed, a precharge signal is first generated so that each pair of bit lines are precharged. A predetermined time after, a row control signal is generated and therefore, one of word lines is selected. Then, read signals on each pair of bit lines are amplified by a sense amplifier. After the read signals on a pair of bit lines are amplified and distinguished into binary logic levels, a column enable signal is generated and a selected pair of bit lines are connected to a pair of bus lines. Then, data on the bus lines is outputted by an output circuit.
In the case of a write, the precharge of bit lines, the selection of word lines are sequentially conducted as in the case of a reading operation. While in this case, a write control signal is activated at the same time as the selection of the word lines so that an input buffer is enabled. The input buffer circuit generates the input data on the pair of bus lines after a relatively short time has elapsed from the enable of the input buffer. However, the selective connection of a pair of bit lines to the pair of bus lines is conducted after a relatively large time has elapsed from the selection of word lines as in the case of the read operation. Namely, the timing relation from the change in address inputs to the selection of bit lines in the write operation is fixed in the same manner as in the read operation. Therefore, even the input data is established on the pair of bus lines at a relatively early stage of the write cycle, writing of the input data to the selected pair of bit lines must be delayed until the time when the selection of bit lines is achieved. Thus, a fast write operation cannot be expected in the conventional SRAMs.